As a ferroelectric random access memory that reduces the area of a plate line driving circuit, a ferroelectric random access memory of a cell array type, a TC parallel type, and a unit series-connected type has been proposed (e.g., see D. Takashima et al., “High-density chain Ferroelectric random memory (CFeRAM)” in proc. VLSI Symp. June 1997, pp. 83-84). Both ends of a ferroelectric capacitor (C) are connected to the source and the drain of a cell transistor (T) to configure a unit. A plurality of unit cells is connected in series to configure a cell block.
The ferroelectric random access memory is a data destructive read type memory that takes out and reads the electric charge of the capacitor. To hold read data, as in the refresh operation of a DRAM, the data are required to be rewritten (written back) to a memory cell. However, in the event of power-down before performing rewrite during read of the data, the data remains destroyed and is lost.